Binary or BCD adder with precorrected result

ABSTRACT

An adder provides either binary or binary coded decimal operation under the selection of a control input. The data inputs are a pair of four bit operands and a carry in for providing an additional capability of greater than four bits. Outputs, in addition to the four bit result, include carry propagate and carry generate signals for the four bit group. Binary operation is conventional. For binary coded decimal operation, the adder corrects an initial binary result to the binary coded decimal format by adding six when there is a group carry generate signal present thus forming an intermediate result. This intermediate result is formed before the occurrence of the carry in from a preceding stage. In the final stage of the adder, the intermediate result is incremented to form the final four bit result if there is a carry in.

This is a continuation of application Ser. No. 860,510, filed Dec. 15,1977, now abandoned, which is a continuation of application Ser. No.664,460 filed Mar. 8, 1976, now abandoned.

BACKGROUND OF THE INVENTION

This invention pertains in general to digital adder circuits and inparticular to an adder for binary or binary coded decimal operands.

In digital computers, addition is one of the most fundamental operationsand the wide spread development of various types of digital computershas correspondingly resulted in the development of a wide variety ofcircuits and techniques for performing addition. Since most digitalcomputers function by manipulating data and instructions expressed asbinary numbers, most digital logic and circuit developments relating toaddition concern the addition of binary numbers. As is well known, thespeed with which binary operands can be added is primarily determined bythe speed with which carries generated by the addition of individualbinary digits can be propagated. Various techniques and circuits forreducing this carry propagation delay time have been developed. The mostwidely used method for high speed binary addition is commonly referredto as look ahead carry addition. The basic principle of look ahead carryaddition is the examination of a number of inputs to each adder stageand the simultaneous production of the proper carries for each of thesestages. The application of the carries to the adder block for each stagethen produces the proper sum bits. Depending upon the number of lookahead carry levels, the overall add time can be significantly reduced.Although the digital circuitry used in computers make the binaryrepresentation of numbers and binary arithmetic the most straightforwardapproach to solving arithmetic problems, human interface requirementsoften dictate the use of decimal representation of numbers. Thus, mostmodern computers provide a capability of operating with both binarynumbers and coded decimal numbers such as binary coded decimal (BCD). Atlow speeds, arithmetic operations involving BCD numbers can be performedwith the same hardware which is used to perform binary arithmetic byusing software algorithms. If computing speed requirements preclude theuse of software algorithms, special digital circuits particularlyadapted to BCD arithmetic must be used. One such technique which usesdigital circuits specifically designed to perform only BCD arithmetic isdescribed in the paper "High Speed Decimal Addition" by Schmoockler andWeinberger published in the IEEE Transactions on Computers, Volume C20,Number 8, August, 1971. Although this approach gives high speed additioncapability for BCD numbers, it requires circuitry that is dedicated onlyfor this purpose and therefore implies additional cost in machines whichmust also perform binary operations.

Another approach to the problem of BCD addition is to perform additionon the BCD operands as though they were binary numbers to form anintermediate result and then correcting this result to form the correctBCD digit of the sum. The usual method for correcting the intermediateresult is to add binary 6. The basis for this method is explained in thetextbook "Arithmetic Operations in Digital Computers" by R. K. Richards,D. Van Nostrand Co., Inc., Princeton, N.J., 1955 pp 210-211. Althoughthis approach offers circuit advantages relating to the fact thatportions of the logic circuits required for binary arithmetic operationscan also be used for BCD arithmetic, it has limitations with respect tospeed. These limitations arise because the time required to add the BCDoperands to form an intermediate result depends upon the carrypropagation delay time. The total time required to obtain the correctBCD representation of the sum thus includes the time required to formthe intermediate result and the time required to apply the BCDcorrection factor so that BCD addition is inherently slower than binaryaddition.

SUMMARY OF THE INVENTION

Accordingly, it is an object of this invention to provide an improvedadder circuit for binary coded decimal numbers.

It is a further object of this invention to provide an improved addercircuit for forming the sum of binary or of binary coded decimaloperands in which the correction factor required for binary codeddecimal addition is applied to a preliminary result before theoccurrence of a carry-in signal from previous adder stage.

Briefly described, the present invention is an adder circuit for binaryor binary coded decimal addition in which binary coded decimal additionis performed by adding the operands as binary numbers without carry-into obtain a first result, applying a correction factor as requiredbefore carry-in is present to obtain a second result and incrementingthe second result with carry-in to obtain the correct binary codeddecimal digit of the sum.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block diagram of a binary/BCD adder according to thepresent invention.

FIG. 2 shows a block diagram of an adder system incorporating aplurality of adders of the type shown in FIG. 1.

FIGS. 3a and 3b show a detailed logic schematic of a binary/BCD adderaccording to the present invention.

DETAILED DESCRIPTION

FIG. 1 shows a block diagram of a binary/BCD adder circuit 10 which is aparticular embodiment of the present invention. Adder circuit 10comprises a binary adder 12 which coupled to input conductors 14, 16, 18and 20 which are the inputs for a four bit A operand and inputs 22, 24,26, 28 which are the inputs for a four bit B operand. Binary adder 12couples to group carry generate and propagate circuit 30 via conductors32 through 46 which are the bit carry generate and carry propagatesignals from binary adder circuit 12. Binary adder circuit 12 alsocouples to precorrection logic circuit 48 via conductors 50, 52, 54 and56 which transmit the first result formed by binary adder 12. Groupcarry generate and propagate circuit 30 couples to conductor 58 which isthe BCD or binary selection control input for adder circuit 10. Circuit30 produces a group carry propagate output on conductor 60 which couplesto incrementer 62 and to look ahead carry logic external to circuit 10.Circuit 30 also provides a group carry generate output on conductor 64which couples to precorrection logic 48, to incrementer 62 and tolook-ahead carry logic external to circuit 10. Precorrection logic 48couples to incrementer 62 via conductors 66, 68, 70 and 72 whichtransmit the second result formed by precorrection logic 48. Incrementer62 couples to output conductors 74, 76, 78 and 80 which form the finalbinary or BCD sum of circuit 10. Incrementer 62 also couples toconductor 82 which is the carry in input to circuit 10.

FIG. 2 shows a partial system block diagram 100 illustrating anembodiment in which a plurality of adder circuits of the type shown inFIG. 1 can be incorporated to form an adder system for adding groups ofBCD numbers or larger binary numbers. Adder system 100 comprises X adder102, Y adder 104 and Z adder 106. X adder 102 has as inputs four bitoperand AX and four bit operand BX which are combined to form four bitsum SX and group carry generate and carry propagate signals onconductors 108 and 110 which couple to look-ahead carry logic 112. Xadder 102 also has as an input input carry CX which couples tolook-ahead carry logic 112 and a BCD control input which couples tocontrol conductor 114. Similarly, Y adder 104 has as inputs four bitoperand AY and four bit operand BY, which are combined to form four bitsum SY and group carry generate and group carry propagate signals onconductor 116 and 118 respectively which couples to look ahead carrylogic 112. Y adder 102 also has a carry-in input CY which couples tolook-ahead carry logic 112 and a BCD control input which couples tocontrol conductor 114. Adder 106 has as inputs four bit operand AZ andfour bit operand BZ which are combined to form four bit sum SZ and groupcarry generate and group carry propagate signals on conductors 120 and122, respectively, which couple to look-ahead carry logic 112. Z adder106 also has a carry in input CZ which couples to look-ahead carry logic112 and a BCD control input which couples to control conductor 114.

FIGS. 3a and 3b show a detailed logic diagram which is one particularembodiment of adder circuit 10 shown in block diagram form in FIG. 1.

FIG. 3a shows group carry generate and propagate circuit 30 which hasbit carry generate and carry propagate signals as inputs on conductors32 through 46 and a BCD/binary control input signal on conductor 58 andproduces as outputs the group carry propagate signal on conductor 60 andthe group carry generate signal on conductor 64. FIG. 3b shows binaryadder 12 which has as inputs operand A on conductors 14, 16, 18 and 20and operand B on conductors 22, 24, 26 and 28. FIG. 3b also showsprecorrection logic 48 coupled to binary adder 12 and also coupled toincrementer 62 which has as an output sum S on conductors 74, 76, 78 and80. A carry in signal from a previous stage couples to incrementer 62via conductor 82. FIG. 3b also shows logic elements for generating acarry out signal which are not shown in FIG. 1. The carry in signal onconductor 82 couples to one input of AND gate 61 while the grouppropagate signal on conductor 60 couples to another input of AND gate 61whose output then couples to an input of OR gate 65. The group carrygenerate signal on conductor 64 couples to another input of OR gate 65whose output couples to conductor 67 which is the carry out signal. Thecarry out signal is used in applications where the adder circuit ofFIGS. 3a and 3b is connected as a ripple adder rather than using lookahead carry logic.

The mode of operation of the present invention is understood by firstconsidering the system block diagram of FIG. 2. FIG. 2 shows a group ofadder circuits arranged to add numbers which may be represented asbinary numbers or as BCD numbers. Logic circuitry internal to each addercircuit responds to the logic state of BCD control conductor 114 todetermine whether the input operands (AX,BX,AY,BY, etc.) will be treatedas binary numbers or as BCD numbers. The system of FIG. 2 includeslook-ahead carry logic 112 to obtain higher adding speeds. This logichas as inputs the group carry propagate and group carry generateconductors from each of the adder circuits and produces as outputs thecarry in signals to each adder circuit. Depending upon the logic stateof BCD control conductor 114, each adder circuit will produce signals onthe group carry propagate and group carry generate conductorsappropriate for either binary or BCD addition. For example, assuming aBCD mode of operation, Y adder 104 will produce a group carry propagatesignal on conductor 116 when the sum of operand AY and BY is equal to 9,indicating to look-ahead carry logic 112 that a carry in to Y adder 104should be propagated to Z adder 106. Similarly, Y adder 104 will producea group carry generate signal on conductor 118 when the sum of operandsAY and BY is greater than 9, indicating that a carry in to Z adder 106should be generated. If a binary mode of operation is assumed, Y adder104 will produce a group carry propagate signal when the sum of operandsAY and BY is equal to 15 and a group carry generate signal when the sumof operands AY and BY is greater than 15. It is important to note thatalthough the use of group carry generate and propagate signals speeds upaddition by allowing the carry inputs for each group to be formulatedsimultaneously, the final sum (for example, SY of Y adder 104) cannot beformed until the carry input has been generated by the look-ahead carrylogic and applied to the adder circuit.

Next, the addition of BCD numbers using binary techniques is consideredas is best illustrated by an example. Assume it is required to form thesum;

    ______________________________________                                                      258                                                                          +498                                                                           756                                                             ______________________________________                                    

Each digit of the operands are represented as BCD numbers and the BCDadder circuit must correctly form the BCD representation of thecorresponding sum digit. Focusing on the middle digits of the above sum,one method which uses binary techniques uses the following step:

STEP 1

Add the BCD operand digits and the carry digit as binary numbers to forma first result

    ______________________________________                                         0101            A operand (=5)                                                1001            B operand (=9)                                               +  1             Carry     (=1)                                                1111            First Result                                                 ______________________________________                                    

Note that the first result is not a valid BCD code which is indicativeof the correction procedure accomplished by the next step.

STEP 2

Compare the first result to binary 9. If the first result is less thanor equal to 9, the first result is the correct BCD digit of the sum. Ifthe first result is greater than 9, add binary 6 to the first result toobtain the correct BCD digit of the sum.

    ______________________________________                                        1111            First Result                                                  0110            Correction Factor                                             0101            BCD Sum Digit (=5)                                            ______________________________________                                    

Note that the most significant bit of the sum is ignored.

A significant limitation in the above method is the fact that the firstresult cannot be formulated until after the carry in from a previousstage is available. Thus, even though carry look-ahead techniques reducethe carry propagation time, the time required to form the final BCDdigit of the sum must include all of the carry propagation time plus theadditional time for applying a correction factor (by adding binary 6).

The heart of the present invention resides in the fact that iteliminates the limitation described above. The manner in which this isaccomplished is conveniently illustrated by repeating the numericalexample given above showing the modified sequence of stepsrepresentative of the present invention.

STEP 1

Add the BCD operand digits as binary numbers (without a carry digit) toform a first result.

    ______________________________________                                        0101             A operand (=5)                                               1001             B operand (=9)                                               1110             First Result                                                 ______________________________________                                    

Again note that the first result is not a valid BCD code which is thusindicative of the correction procedure accomplished by the next step.

STEP 2

Compare the first result to binary 9 and add an appropriate correctionfactor to the first result to form a second result. If the first resultis less than or equal to 9, the correction factor is 0. If the firstresult is greater than 9, the correction factor is 6.

    ______________________________________                                        1110             First Result                                                 0110             Correction Factor                                            0100             Second Result                                                ______________________________________                                    

Again note that the most significant bit of the second result isignored.

STEP 3

Increment the second result with carry-in to obtain the correct BCDdigit of the sum

    ______________________________________                                        0100            Second Result                                                   1             Carry In                                                      0101            BCD Sum Digit                                                 ______________________________________                                    

In performing Step 3 for BCD addition, the second result must beincremented to the next sequential BCD digit, i.e., 7, 8, 9, 0, 1, 2,etc.

The above example illustrates two key advantages of the presentinvention. First, the addition of the correction factor required for aparticular BCD digit is performed before the input carry for thatparticular digit is generated by the look-ahead carry logic. Thisoverlapping of operations significantly reduces the amount of timerequired to add digits in the BCD mode. Second, the use of a finalincrementing step to incorporate carry in for forming the final BCD sumallows simpler circuit implementation which can operate at higher speedsthan the circuits required for a complete addition step.

FIG. 1 shows an adder circuit 10 according to the present inventionwhich performs BCD addition as illustrated in the above example. Addercircuit 10 is arranged to add in either the BCD mode or the binary modeas defined by the logic state of BCD control conductor 58. In the BCDmode, the A operand and the B operand are each 4 bit BCD numbers. Binaryadder 12 adds these numbers as binary numbers to form a 4 bit firstresult on conductors 50, 52, 54 and 56 as illustrated in Step 4 of theabove example. Binary adder 12 also produces individual bit carrypropagate and carry generate signals on conductors 32-46 therebyproviding the inputs required by circuit 30 to produce the group carrygenerate and group carry propagate signals required by lookahead carrylogic. Pre-correction logic 48 applies a correction factor to the 4 bitfirst result on conductors 50, 52, 54 and 56 to form a 4 bit secondresult on conductors 66, 68, 70 and 72 as illustrated in Step 2 of theabove example. For the BCD mode, the group carry generate signal onconductor 64 determines whether the required correction factor is binary0 or binary 6. Incrementor circuit 62 responds to the carry in signal onconductor 82 to increment the second result on conductors 66, 68, 70 and72 by 1 thereby forming the final BCD sum S on conductors 74, 76, 78 and80 as illustrated in Step 3 of the above example. Another majoradvantage of the present invention as shown by the block diagram of FIG.1 is the fact that major portions of the logic circuitry are the samefor addition in the BCD mode and addition in the binary mode. Thus, thecircuitry and operation of binary adder 12 is the same for either BCD orbinary addition. Major portions of circuit 30 are the same for eitheradding mode with the BCD control conductor 58 enabling logic in circuit30 to produce group carry generate and group carry propagate signals onconductors 64 and 60 respectively appropriate for the given mode andthereby also providing appropriate adding mode control forpre-correction logic 48 and incrementor 62. Since the "pre-correctionfactor" required for addition in the binary mode is always binary 0which is the same as one of the factors required for the BCD mode, thecircuitry required for pre-correction logic 48 is the same for bothmodes. Finally, incrementor 62 performs the same basic function in eachaddition mode with control information on conductors 60 and 64conditioning incrementor 62 to function as a BCD incrementor (7, 8, 9,0, 1, 2, . . .) or as a binary incrementor (13, 14, 15, 0, 1, 2,).

The above features of the invention offer significant advantages inproviding an adder with both binary and BCD capability which has greatlyreduced circuit complexity and improved operating speed. Theseadvantages are particularly important in monolithic integrated circuitembodiments. In one such embodiment, using the circuit organizationshown in FIG. 1, the combined binary and BCD addition capability wasobtained with only a 4% increase in component count from that requiredfor a binary capability alone. Also, the embodiment of FIG. 1 resultedin BCD addition speeds which were equal to binary addition speeds--a 30%to 40% improvement over the speeds obtained by the conventional approachillustrated by the first numerical example above.

What is claimed is:
 1. An adder circuit for forming the BCD sum of afirst BCD digit and a second BCD digit comprising:a. means for addingsaid first and second BCD digits as binary numbers without carry-in toform a first result; b. means for adding a BCD correction factor to saidfirst result without carry-in to form a second result; and c. means forincrementing said second result by one in response to a carry-in signalto form said BCD sum.
 2. An adder circuit for forming the BCD sum of afirst BCD operand and a second BCD operand comprising:a. means foradding the corresponding digits of said operands as binary numberswithout carry-in to form a set of first results; b. means for adding aBCD pre-correction factor to each said first result without carry-in toform a set of second results; and c. means for incrementing each saidsecond result by decimal one in response to a carry-in signal to formthe digits of said BCD sum.
 3. An adder circuit as recited in claim 2wherein said BCD pre-correction factor is binary six if said firstresult is greater than nine and said BCD pre-correction factor is binaryzero otherwise.
 4. The adder circuit recited in claim 3 wherein saidmeans for adding the digits of said first and said second BCD operandscomprise a binary adder circuit without carry-in.
 5. The adder circuitrecited in claim 4 further comprising group carry generate and propagatemeans coupled to said binary adder circuit for generating a group carrygenerate signal and a group carry propagate signal to facilitatelookahead carry addition.
 6. The adder circuit recited in claim 5further comprising BCD control means coupled to said group carrygenerate and propagate means, to said means for adding a BCDpre-correction factor and to said means for incrementing, for convertingthe operation of the adder circuit to form the binary sum of a first anda second binary operand.